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A Fast VLSI Implementation of a FIFO Queue
Berry, D and Headlam, A and Loane, RK and Parry, J and Wang, TK and Sale, AHJ (1987) A Fast VLSI Implementation of a FIFO Queue. In: Microelectronics Conference VLSI 1987, 8-10 April 1987, Melbourne, Australia.
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Available under University of Tasmania Standard License.
The paper describes a hardware implementation in nMOS of a first-in, first-out (FIFO) queue. The implementation has independently operating insertion and extraction logic which is capable of achieving high speeds of less than 20Ons per operation, and may be entirely contained on a single chip. A regular cellular structure is described which is capable of extension both in the direction of wider queued items and in the direction of maximum queue size. The implementation was carried out at the University of Tasmania by the first five authors under the supervision of the last-named author.
|Item Type:||Conference or Workshop Item (Paper)|
|Keywords:||FIFO queue, hardware, chip inplementation|
|Publisher:||The Institution of Engineers, Australia|
|Page Range:||pp. 96-100|
|Date Deposited:||04 Jan 2005|
|Last Modified:||18 Nov 2014 03:10|
|Item Statistics:||View statistics for this item|
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