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NAIAD: A Dual-Purpose Bit-Slice Processor
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Available under University of Tasmania Standard License.
Using bit-slice components, a variable architecture processor has been designed to serve two purposes: to teach microprogramming and computer architecture to undergraduate students and to form the processing element of a dataflow machine. Microcode is loaded using a serial-protocol channel which can also be used for debugging: the current word in the MAP RAM and the pipeline register can be read at every clock cycle. The processor is provided with sufficient local memory (128K 32-bit words) to store test programs and data for teaching or a large segment of a dataflow program graph. In a dataflow processor, the design permits experimentation with operation granularity and provides a number of mechanisms for transferring program instructions to the processor - via the instruction stream, by loading new microcode and by transferring program segments to the local memory.
|Item Type:||Conference or Workshop Item (Paper)|
|Keywords:||bit-slice, computer architecture, dataflow|
|Page Range:||pp. 803-813|
|Date Deposited:||06 Jan 2005|
|Last Modified:||18 Nov 2014 03:10|
|Item Statistics:||View statistics for this item|
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