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Validation and Verification of Software Design using Finite State Process
Stanton, SC (2002) Validation and Verification of Software Design using Finite State Process. Honours thesis, University of Tasmania.
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This thesis aims to evaluate the effectiveness of a formal language (Finite State Process) automated verification tool (Labelled Transition System Analyser) at finding and resolving errors in design models of software. FSP is used to model the Lift Problem from a specification refined by validation. The specification is mapped to a finite state domain and tested for errors - in the mapping, in the understanding of the initial requirements, in the accuracy of the initial requirements, and in the concurrency properties of the identified co-operating entities. Exposition of errors refines (validates) the initial description, and drives their resolution giving rise to an evolutionary corrected model; upon exit of iterative analysis this is mapped to UML behavioural diagrams forming Implementation Specifications.
|Item Type:||Thesis (Honours)|
|Keywords:||Finite state process, Object oriented design, verification, model checking|
|Publisher:||Honours thesis, University of Tasmania|
|Date Deposited:||12 Aug 2004|
|Last Modified:||18 Nov 2014 03:10|
|Item Statistics:||View statistics for this item|
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